The Low Level Blog

    • Privacy Policy
    • Welcome!
  • The secret way to disable interrupts – Arcane x86 (#2)

    September 4, 2025
    Arcane x86

    The x86 supports hardware interrupts (like nearly every other CPU does) – the ability for a device such as a keyboard, disk, network card, internal timer, etc. to notify the CPU when something needs to be actioned (e.g. a key was pressed, some data is ready). An interrupt will cause the CPU to stop what…

  • XLAT, the most specific instruction – Arcane x86 (#1)

    September 3, 2025
    Arcane x86

    The x86 ISA is very flexible in terms of addressing modes. To form an address you can add two registers together (one of them optionally multiplied by 2, 4 or 8), and then add an offset! And (nearly) every subset of these features can be used also. For instance, these are all valid addressing modes:…

  • Welcome!

    September 3, 2025
    Arcane x86

    Welcome to The Low Level Blog! When tutoring a university course on CPU design, I found myself sharing with a group of students all the strange and mysterious corners of the x86 ISA, giving them a new obscure fact each week. A year and half later, I’ve decided to start a blog, just sharing this…

The Low Level Blog

  • Instagram
  • Facebook
  • X